In the semiconductor industry, the use of electrostatic discharge protection (ESD) circuits is known. ESD circuits ensure that integrated semiconductor devices are not destroyed by static electricity during routine post-manufacture processes.
FIG. 1 depicts a prior art diagram of an electrical system 10. Electrical system 10 consists of a human body model tester 12 and an integrated circuit 13. Human body model tester 12 itself consists of a power supply 14, a capacitor 16, switches 15 and 17, a resistor 18, and a system ground 20. A first terminal of power supply 14 is connected to system ground 20. A second terminal of power supply 14 is connected to a first terminal of switch 15. A first terminal and a second terminal of capacitor 16 are coupled in to system ground 20 and to a second terminal of switch 15. A first terminal of switch 17 is connected to the second terminal of switch 15. A second terminal of switch 17 is connected to a first terminal of resistor 18. A second terminal of resistor 18 and system ground 20 are the two outputs of human body model tester 12.
Human body model tester 12 synthesizes the effects of a human body handling integrated circuit 13. After manufacture, it is possible for a person to pick up integrated circuit 13 by making a connection between any two pins on the integrated circuit with the person's hand. When this occurs, any static electricity built-up in the body will discharge through the part via the contacted pins. Human body model tester 12 models such a condition by asymmetrically opening and closing switches 15 and 17 while the two outputs of human body model tester 12 are connected to two pins of integrated circuit 13. In this way, an electric charge is stored in capacitor 16 and subsequently discharged to integrated circuit 13 through resistor 18. The amount of charge stored in capacitor 16 may be slowly increased to increase the output ESD until integrated circuit 13 fails or meets some predetermined criteria. In this way, human body model tester 12 can methodically determine the robustness of integrated circuit 13 to ESD.
Integrated circuit 13 consists of an I/O terminal 22, a low voltage supply GND 24, diodes 26 and 28, a high voltage supply VDD 30, a P-type transistor 32, an N-type transistor 34, and an input buffer 36. I/O terminal 22 is connected to a P-type terminal of diode 26 and an N-type terminal of diode 28. The N-type terminal of diode 26 is connected to voltage supply VDD 30. The P-type terminal of diode 28 is connected to voltage supply GND 24. A first current electrode and a second current electrode of transistor 32 are connected to I/O terminal 22 and to voltage supply 30, respectively. A first current electrode and a second current electrode of transistor 34 is connected to I/O terminal 22 and to voltage supply 24, respectively. An input of input buffer 36 is connected to I/O terminal 22. An output of input buffer 36 generates the data signal labeled in FIG. 1 DATA IN.
During normal operation, an input voltage is driven onto I/O terminal 22 to input buffer 36 by an external device (not shown) or an output voltage is driven off of I/O terminal 22 by one of transistors 32 and 34. In either case, the voltage on I/O terminal 22 would approximate either voltage supply GND 24 or voltage supply VDD 30. If a high signal were applied at I/O terminal 22, then diode 26 would not be forward biased nor would the breakdown voltage of diode 28 be exceeded. Therefore, no "leakage" current would flow through diodes 26 and 28. Conversely, if a low signal were applied to I/O terminal 22, then neither of diodes 26 or 28 would be forward biased. Again, diodes 26 and 28 would not leak current during normal operation.
During an ESD event, voltages significantly higher than the difference between voltage supply VDD 30 and voltage supply GND 24 are applied to the inputs of integrated circuit 13. For example, when a large positive voltage is applied between I/O terminal 22 and voltage supply VDD 30, diode 26 becomes strongly forward biased and current will flow from I/O terminal 22 through diode 26 to voltage supply VDD 30. Excessive charge is thereby diverted from transistors 32 and 34 and from input buffer 36. Conversely, a large negative charge may be applied between I/O terminal 22 and voltage supply GND 24. In this case, diode 28 becomes strongly forward biased and current will flow from voltage supply GND 24 through diode 28 to I/O terminal 22. Excessive charge is again diverted.
Although the ESD protection provided by diodes 26 and 28 is effective, integrated circuit 13 is not tolerant of inputs greater than one diode drop above voltage supply VDD 30. Typically, it is advantageous for integrated circuit 13 to operate at a certain low voltage, e.g. 3.3 volts, yet tolerate input signals of a higher level, e.g. 5 volts. If such an input were applied to I/O terminal 22, then leakage current would flow from through diode 26 as diode 26 attempted to clamp I/O terminal 22 at one diode drop above voltage supply VDD 30. This leakage current would be unacceptable. Also, transistors 32 and, especially, 34 might be damaged by the application of 5 volts between their first current electrodes and their control electrodes.
Prior art FIG. 2 illustrates a second embodiment of electrical system 10 having a human body model tester 12 and an integrated circuit 13. The human body model tester 12 is identical to that of FIG. 1 and will not be discussed further. Here, a diode string 40 of five diodes replaces diode 26. A N-terminal of diode string 40 is connected to voltage supply VDD 30. A P-terminal of diode string 40 is connected to I/O terminal 22. An N-type transistor 38 is also coupled in series between I/O terminal 22 and the first current electrode of transistor 38. A control electrode of transistor 38 is connected to voltage supply VDD 30.
During normal operation, an input voltage larger than voltage supply VDD 30 can be applied to I/O terminal 22. Such a configuration allows for integrated circuits requiring different power supplies to be connected together directly. Diode string 40 will not leak current until the input voltage is 5 diode drops above voltage supply VDD 30. Typically, this difference is sufficient to make a 3.3 volt device 5 volt tolerant. Transistor 38 ensures that the 5 volt signal received at I/O terminal 22 is not directly seen by transistor 34. (In the depicted embodiment, N-type transistor 34 is less robust than P-type transistor 32.) In particular, the maximum voltage difference across the first current electrode and control electrode of transistor 38 is 1.7 volts (5-3.3). Continuing away from I/O terminal 22, the voltage output by the second current electrode of transistor 38 is the one threshold voltage less than the voltage applied to the control electrode of transistor 38, approximately 2.8 volts. Consequently, the maximum voltage difference across the first current electrode and control electrode of transistor 34 is 2.8 volts (2.8-0). All of these voltages are tolerable within 3.3 volt devices.
During an ESD event, diode string 40 operates as does diode 26 depicted in FIG. 1, becoming forward biased when a voltage larger than voltage supply VDD 30 plus five diode drops is applied to I/O terminal 22. Diode string 40 can then shunt charge excessive charge from input buffer 36 and transistors 32, 34, and 38.
Unfortunately, diode chain 40 also behaves like a Darlington chain of parasitic bipolar transistors during normal operation. In a Darlington chain, the gain or .beta. of each transistor amplifies the leakage current of the previous transistor. As a result, diode string 40 will be characterized by a large leakage current unless .beta. is very small. The gain or .beta. of a transistor is dependent upon process used to manufacture integrated circuit 13 and may be difficult to control.
Prior art FIG. 3 illustrates a third embodiment of electrical system 10. Human body model tester 12 is the same as in prior art FIG. 1. Integrated circuit 13 comprises a PNP transistor 42, a P-type transistor 44, an NPN transistor 46, and a PNP transistor 48 in place of diodes 26 and 28 (depicted in FIG. 1). A first current electrode and a second current electrode of transistor 42 are connected to I/O terminal 22 and to voltage supply 30, respectively. A first current electrode, a second current electrode, and a control electrode of transistor 44 are connected to the control electrode of transistor 42, to voltage supply VDD 30, and to I/O terminal 22, respectively. A first current electrode, a second current electrode, and a control electrode of transistor 46 are connected to I/O terminal 22, to the voltage supply VDD 30, and to voltage supply GND 24, respectively. A first current electrode, a second current electrode, and a control electrode of transistor 48 are connected to I/O terminal 22, to voltage supply GND 24, and to the control electrode of transistor 42, respectively.
During normal operation, either a 5 or 0 volt input would be applied to I/O terminal 22. A 5 volt input would turn-off transistor 44, allowing the control electrodes of transistors 42 and 48 to follow the input voltage less one diode drop. A 0 volt input would turn-on transistor 44 thereby applying voltage supply VDD 30 to the control electrodes of transistors 42 and 48. In this case, these transistors would be in a non-conducting state. In either case, integrated circuit 13 would generate little or no leakage current during normal operation.
During an ESD event, either a large positive or a large negative charge is applied to I/O terminal 22 with respect to voltage supply GND 24 or with respect to voltage supply VDD 30. In the case of a large positive input, transistor 44 is turned-off, allowing the control electrodes of transistors 42 and 48 to follow the input voltage less one diode drop. However, transistor 44 will enter into gate aided junction breakdown because of the large voltage difference between its control electrode and voltage supply VDD 30. In gate aided junction breakdown, current flows from the current electrode to (or from) the silicon below the control electrode of the transistor. Here, the silicon below the control electrode of transistor 44 is an N-well which is also the control electrode of PNP transistors 42 and 48. This current becomes the base current of transistor 42 if the ESD event is with respect to I/O terminal 22 and voltage supply VDD 30. Or, this current becomes the base current of transistor 48 if the ESD event is with respect to I/O terminal 22 and voltage supply GND 24. Transistors 42 and 48 amplify the base current applied to them by their respective gains or .beta.'s. This current then shunts the excessive charge to the appropriate voltage supply. In the case of a large negative input, transistor 46 becomes forward biased with respect to one voltage supply. If the ESD event is with respect to I/O terminal 22 and voltage supply GND 24, then excess charge flows from voltage supply GND 24 through the control electrode and the first current electrode of transistor 46 to I/O terminal 22. If the ESD event is with respect to I/O terminal 22 and voltage supply VDD 30, then excess charge flows from voltage supply VDD 30 through the inherent capacitance of integrated circuit 13 to voltage supply GND 24 and then out through I/O terminal 22.
The ESD protection afforded by integrated circuit 13 depends in large part upon transistor 44 entering gate aided junction breakdown near or prior to transistors 32, 34, or 38 entering into gate aided junction breakdown. As described above, the current generated by transistor 44 becomes the base current for transistors 42 and 48. If transistors 32, 34, or 38 enter gate aided junction breakdown first, then they may continue into secondary breakdown before transistor 44 begins supplying base current to transistors 42 and 48. In secondary breakdown, excessive current flows through a transistor heats it, melts it, and permanently impairs its ability to function. In the embodiment depicted in FIG. 3, transistor 44 will begin supplying drive current at approximately the same time as transistor 32 enters into gate aided junction breakdown, the voltage "BVDSSP." These transistors are the same conductivity type and, hence, behave identically. Transistor 44 is not the same conductivity type as transistors 34 and 38. Transistors 34 and 38 enter gate aided junction breakdown at the voltage "BVDSSN." Therefore, the ESD circuit depicted here will only protect integrated circuit 13 if BVDSSP is less than BVDSSN. Unfortunately, the relationship between BVDSSN and BVDSSP is process dependent. Therefore, each new instantiation of integrated circuit 13 may require a different ESD circuit. This requirement can become difficult to bare as integrated circuit 13 is reduced in size, or is otherwise manufactured according to a new process recipe.